(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an elevated source/drain with solid phase diffused source/drain extensions for improved performance of deep submicron MOSFETS in the fabrication of integrated circuits.
(2) Description of the Prior Art
As integrated circuit devices become smaller, especially in the deep submicron regime, performance concerns become more pressing. In particular, a shallow junction is desired in deep submicron integrated circuit devices because shallow junctions provide a smaller short channel effect and larger punch through voltage. It is difficult to implement a shallow junction with source/drain ion implantation. Usually, a deep junction results from ion implantation. FIG. 1 illustrates a partially completed integrated circuit having a gate electrode 18 formed over a gate oxide layer 16 on a semiconductor substrate 10. Ion implantation 51 forms deep junctions 53. Shallow junctions 55 are formed lightly doped drain (LDD) ion implant before sidewall spacer 19 formation. However, even with the LDD ion implant, ultra shallow junction depth cannot be achieved.
FIG. 2 illustrates another prior art process. In this process, shallow junctions 57 are formed by solid phase diffusion of impurities from a deposited phosphosilicate glass (PSG) or borosilicate glass (BSG) into the semiconductor substrate. However, since the entire region of the source and drain is very shallow, the metallurgy to contact the source or drain will penetrate through the source or drain resulting in a junction short.
Using an elevated source/drain structure, the junction can be formed above the silicon surface. This allows the junction depth to be ultra shallow. In addition, due to the elevated source/drain, the source/drain has enough thickness to support the consumption of metallization.
FIG. 3 illustrates a process in which elevated source/drain regions 59 are formed. The problem with this approach is that the source/drain regions 59 may not connect with the channel region 63 because of the presence of the sidewall spacers 19. Also, if the drive-in step is too long, the junction 61 will be too deep for the source/drain to channel connection. If the junctions 65, illustrated in FIG. 4, are formed by lightly doped source and drain ion implantation before the formation of the elevated source/drain regions, the thermal budget of the selective epitaxial growth used to form the elevated source/drain will drive-in the source/drain dopant too deeply into the substrate.
In order to resolve the problems stated above, disposable spacer technology has been tried. U.S. Pat. No. 5,296,727 to Kawai et al and the article, "Reverse Elevated Source/Drain (RESD) MOSFET for Deep Submicron CMOS," by J. R. Pfiester et al, IEDM 1992, pp. 885-888, teach methods of forming reverse and elevated source/drain regions. As illustrated in FIG. 5, after formation of the elevated source/drain 59, the gate electrode sidewall spacers are removed. Ions 67 are implanted through the openings to the substrate to form lightly doped source and drain regions 69. However, this process could be quite complicated.
It is desirable to provide a simple process of source/drain formation that can achieve high performance especially in deep submicron MOSFET integrated circuits.